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CXD3300R 10-bit 20msps video a/d converter description the CXD3300R is a 10-bit cmos a/d converter for video applications. this ic is ideally suited for the a/d conversion of video signals in tvs, vcrs, camcorders, etc. features resolution: 10 bits 1.0lsb (d.l.e.) maximum sampling frequency: 20msps low power consumption: 40mw (except self-bias ) low input capacitance built-in self-bias circuit absolute maximum ratings (ta = 25?) supply voltage av dd av ss ?0.5 to +4.5 v dv dd dv ss ?0.5 to +4.5 v reference voltage vrt, vrb av dd + 0.5 to av ss ?0.5 v input voltage v in av dd + 0.5 to av ss ?0.5 v (analog) input voltage v ih , v il av dd + 0.5 to av ss ?0.5 v (digital) output voltage v oh , v ol dv dd + 0.5 to dv ss ?0.5 v (digital) storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 3.0 0.3 v dv dd , dv ss 3.0 0.3 v | dv ss ?av ss | 0 to 100 mv reference input voltage vrb 0.3av dd to 0.5av dd v vrt 0.6av dd to 0.8av dd v analog input v in 0.9vp-p or more clock pulse width t pw 1 25 (min.) ns t pw 0 25 (min.) ns operating ambient temperature topr ?0 to +85 ? ?1 e97310-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin lqfp (plastic) structure silicon gate cmos ic
? 2 CXD3300R a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a 8 d a c c o a r s e c o m p a r a t e & e n c o d e c a l i b r a t i o n u n i t f i n e c o m p a r a t e & e n c o d e f i n e l a t c h c o a r s e c o r r e c t i o n & l a t c h t i m i n g g e n . 2 3 4 5 8 9 1 0 1 1 1 2 1 5 1 8 1 9 2 0 2 2 2 3 2 4 2 7 3 8 4 2 1 a a a a a a a a a a a a a a a a a a a u t o c a l i b r a t i o n p u l s e g e n e r a t o r d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ( l s b ) m i n v l i n v t e s t m o d e c a l r e s e t 3 1 v r t v r t c v r t s v r m c v i n b e v r b s v r b v r b c c l k o e c e s / h a m p 3 0 3 6 3 3 3 2 2 8 2 9 + c e o e c l k a v d d m i n v l i n v t e s t m o d e a v d d a v s s r e s e t t i n t o t s t r v i n t s a v d d a v s s c a l a v d d a t a v d d a v s s d v d d d v s s b e a v d d a v s s v r b s v r b v r b c v r m c v r t c v r t v r t s a v d d a v s s d 1 d 2 d 3 d 4 d v s s d v d d d 5 d 6 d 7 d 8 d 9 d 0 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 pin configuration block diagram
? 3 CXD3300R pin description pin no. symbol equivalent circuit description 1 to 5 8 to 12 d0 to d9 6, 48 dv ss 7, 47 dv dd 13 to 14 tin d0 (lsb) to d9 (msb) output. digital v ss . digital v dd . test pin. high impedance when ts = high. test signal input. normally fixed to av dd or av ss . 15 reset calibration circuit reset and startup calibration restart. 18 testmode test mode. high: output state low: output fixed 16, 25, 34, 41, 46 av ss analog v ss . 17, 21, 26, 35, 40, 43, 45 av dd analog v dd . d v d d d v s s a v d d a v s s 1 5 a v d d a v s s 1 8 19 linv output inversion. high: d0 to d8 are inverted and output. low: d0 to d8 are normal output. a v d d a v s s 1 9
? 4 CXD3300R pin no. symbol equivalent circuit description 20 minv output inversion. high: d9 is inverted and output. low: d9 is normal output. a v d d a v s s 2 0 22 clk clock. a v d d a v s s 2 2 23 oe d0 to d9 output enable. low: output state high: high impedance state a v d d a v s s 2 3 24 ce chip enable. low: active state high: standby state a v d d a v s s 2 4
? 5 CXD3300R pin no. symbol equivalent circuit description self-bias. (reference top) 27 vrts reference top. 28 vrt reference top output. 29 vrtc reference middle output. 30 vrmc reference bottom output. 31 vrbc reference bottom. 32 vrb self-bias. (reference bottom) 33 vrbs bias enable. 36 be a v d d a v s s a v d d a v s s a v d d a v s s a v d d a v s s a v d d a v s s a v d d a v s s a v d d a v s s a v d d a v s s 2 7 2 8 3 3 3 2 2 9 3 0 3 1 3 6
? 6 CXD3300R pin no. symbol equivalent circuit description 37 tstr test signal input. normally fixed to av dd or av ss . 44 at test signal input. high impedance when ts = high. 38 vin analog input. 42 cal calibration pulse input. 39 ts test signal input. normally fixed to av dd . a v d d a v s s 3 8 a v d d a v s s 4 2
? 7 CXD3300R a a a a a a a a a t d l n n + 1 n + 2 n + 3 n + 4 t p w 1 t p w 0 : i n d i c a t e s p o i n t a t w h i c h a n a l o g d a t a i s s a m p l e d c l o c k a n a l o g i n p u t d a t a o u t p u t n 3 n 2 n n 1 1 . 5 v t s d 1 . 5 v digital output the following table shows the correlation between the analog input voltage and the digital output code. (testmode = 1, linv, minv = 0) the following table shows the output state for the combination of testmode, linv, and minv states. input signal voltage digital output code msb lsb vrt vrb 1111111111 1000000000 0111111111 0000000000 1023 512 511 0 testmode linv minv d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 p n p n 1 0 1 0 p n p n 0 1 0 1 p n p n 1 0 1 0 p n p n 1 0 1 0 p n p n 1 0 1 0 p n p n 1 0 1 0 p p n n 0 0 1 1 p n p n 0 1 0 1 p n p n 0 1 0 1 p n p n 0 1 0 1 p: forward-phase output n: inverted output timing chart 1 timing chart 2 h i g h i m p e d a n c e t p e z t p z e a c t i v e a c t i v e 1 . 5 v 1 . 5 v o u t p u t e n a b l e ( o e ) d a t a o u t p u t 1 . 5 v step
? 8 CXD3300R electrical characteristics (fc = 20msps, av dd = 3v, dv dd = 3v, vrb = 1v, vrt = 2v, ta = 25 c) fc max fc min ia dd id dd ia st id st i rt 1 i rb 1 i rt 2 i rb 2 bw c in r ref 1 r ref 2 e ot1 e ob1 e ot2 e ob2 v ih v il a ih a il i ih i il i oh i ol i ozh i ozl t pez t pze e l e d 20 11 87 ?11 1.81 ?.33 9k 430 ?0 ?0 ?0 ?0 0.7av dd 40 ?5 1.0 1.0 6 3 14 1.0 97 97 2.04 ?.04 85 10 10.3k 490 +5 +5 +5 +10 48 ?8 8 5 1.0 0.5 0.5 17 4 3.0 1.0 111 ?7 2.33 1.81 11.5k 550 +40 +40 +40 +40 0.2av dd 55 ?0 5 5 1 1 10 7 3.0 1.0 msps ma ma a a ma mhz pf mv mv v a a ma a ns ns lsb lsb maximum conversion rate minimum conversion rate supply current standby current reference pin current 1 reference pin current 2 analog input band analog input capacitance reference resistance value 1 reference resistance value 2 offset voltage1 offset voltage2 digital input voltage analog input current digital input current digital output current digital output current tri-state output disable time tri-state output enable time integral nonlinearity error differential nonlinearity error f in = 1.0khz sine wave input f in = 1.0khz sine wave input be = high ce = av dd vrts, vrbs: open between vrt and vrb be = av dd between vrtc and vrbc ?db between vrts and vrt, vrt and vrb, vrb and vrbs between vrtc and vrbc be = av dd e ot1 = theoretical value ?measured value e ob1 = measured value ?theoretical value be = av ss e ot2 = theoretical value ?measured value e ob2 = measured value ?theoretical value av dd = 2.7 to 3.3v v in = 2v v in = 1v v ih = av dd av dd = 3.3v v il = av ss oe = av ss v oh = dv dd ?0.4v dv dd = 2.7v v ol = 0.4v oe = av dd v oh = dv dd dv dd = 3.3v v ol = 0v clock not synchronized for active ? high impedance clock not synchronized for high impedance ? active item symbol conditions min. typ. max. unit analog digital analog digital
? 9 CXD3300R snr sfdr 6 6 1.0 0.3 9 7 50 50 50 50 45 44 52 52 52 52 49 50 % deg ns ns 18 8 db db snr sfdr item symbol conditions min. typ. max. unit f in = 100khz f in = 500khz f in = 1mhz f in = 3mhz f in = 7mhz f in = 10mhz f in = 100khz f in = 500khz f in = 1mhz f in = 3mhz f in = 7mhz f in = 10mhz differential gain error differential phase error output data delay sampling delay ntsc 40 ire mod ramp, fc = 14.3msps c l = 3pf, ta = ?0 to +85 c dg dp t dl t sd
? 10 CXD3300R application circuit 1 when not using self-bias and the internal bias circuits, and supplying the reference voltage from an external source. 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 4 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 7 3 9 4 0 4 1 4 2 4 3 4 4 4 7 4 8 t s t r v i n t s a v d d a v s s c a l a v d d a t a v d d a v s s d v d d d v s s c e o e c l k a v d d m i n v l i n v t e s t m o d e a v d d a v s s r e s e t t i n t o b e a v d d a v s s v r b s v r b v r b c v r m c v r t c v r t v r t s a v d d a v s s d 0 d 1 d 2 d 3 d 4 d v s s d v d d d 5 d 6 d 7 d 8 d 9 a v d d a v s s a v d d a v s s : 0 . 1 f a v d d d v d d d v s s a v s s 1 v 2 v a v d d d v s s d v d d 4 6 3 8 1 . 0 v 2 . 0 v c l o c k i n p u t d i g i t a l o u t p u t r e s e t p u l s e c a l i b r a t i o n p u l s e s i g n a l i n p u t application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 11 CXD3300R application circuit 2 when not using self-bias circuit, using only the internal bias circuit, and supplying the reference voltage from an external source. 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 4 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 7 3 9 4 0 4 1 4 2 4 3 4 4 4 7 4 8 t s t r v i n t s a v d d a v s s c a l a v d d a t a v d d a v s s d v d d d v s s c e o e c l k a v d d m i n v l i n v t e s t m o d e a v d d a v s s r e s e t t i n t o b e a v d d a v s s v r b s v r b v r b c v r m c v r t c v r t v r t s a v d d a v s s d 0 d 1 d 2 d 3 d 4 d v s s d v d d d 5 d 6 d 7 d 8 d 9 a v d d a v s s a v d d a v s s : 0 . 1 f a v d d d v d d d v s s a v s s 1 v 2 v a v d d d v s s d v d d 4 6 3 8 1 . 0 v 2 . 0 v a v s s c l o c k i n p u t d i g i t a l o u t p u t r e s e t p u l s e c a l i b r a t i o n p u l s e s i g n a l i n p u t application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 12 CXD3300R application circuit 3 when using the self-bias and internal bias circuits, and supplying the reference voltage. 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 4 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 7 3 9 4 0 4 1 4 2 4 3 4 4 4 7 4 8 t s t r v i n t s a v d d a v s s c a l a v d d a t a v d d a v s s d v d d d v s s c e o e c l k a v d d m i n v l i n v t e s t m o d e a v d d a v s s r e s e t t i n t o b e a v d d a v s s v r b s v r b v r b c v r m c v r t c v r t v r t s a v d d a v s s d 0 d 1 d 2 d 3 d 4 d v s s d v d d d 5 d 6 d 7 d 8 d 9 a v d d a v s s a v d d a v s s : 0 . 1 f a v d d d v d d d v s s a v s s a v d d d v s s d v d d 4 6 3 8 1 . 0 v 2 . 0 v a v s s c l o c k i n p u t d i g i t a l o u t p u t r e s e t p u l s e c a l i b r a t i o n p u l s e s i g n a l i n p u t application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 13 CXD3300R 1. calibration function 1) activating startup calibration to achieve superior linearity, the CXD3300R has a built-in calibration circuit. when using this ic, therefore, startup calibration must be activated when the power supply and reference voltage have risen and stabilized. care should be taken as only the upper five bits may be output in the worst case if startup calibration is not activated. startup calibration can be activated either at the rise of the reset pin (pin 15) or at the fall of the ce pin (pin 24). the startup calibration activation method for each case is shown in fig. 1. a ) w h e n u s i n g r e s e t a v d d v r t v r b [ v ] 3 0 [ t ] r e s e t h l h l 3 3 , 0 0 0 c l k c e s t a r t u p c a l i b r a t i o n b ) w h e n u s i n g c e a v d d v r t v r b [ v ] 3 0 [ t ] r e s e t h l h l 3 3 , 0 0 0 c l k c e s t a r t u p c a l i b r a t i o n fig. 1. startup calibration activation methods as shown in the figure above, startup calibration must be activated after the supply voltage has risen and stabilized (full scale of 90% or more). after activation, startup calibration is performed for an interval of about 33,000 clocks. therefore, care should be taken as the output data during this interval (about 2.3ms at 14.3mhz) cannot be used. 2) calibration pulse supply the ic's operating status with changes due to fluctuations in the supply voltage and ambient temperature during use can be constantly monitored and then compensated appropriately by inputting a pulse at regular intervals to the cal pin (pin 41). fig. 2 shows the timing chart. 7 c l o c k s 1 c l o c k o r m o r e c l k c a l d 0 t o d 9 1 0 n s o r m o r e n 3 n 2 n 1 n n + 5 fig. 2. calibration timing chart
? 14 CXD3300R [2] input every v sync i n p u t c l k r e s e t c a l calibration starts when the fall of the pulse input to the cal pin (pin 41) is detected at the clock rise. at this time, the comparator is used in an exclusive manner for a four clock interval. so, the output data holds the immediately previous data for a four clock interval after seven clocks from the rise of the clock where the fall of the calibration pulse was detected, and then the data during this interval is missing. therefore, the effects of this function can be avoided by inputting a sync or other signal as the calibration pulse so that calibration is performed outside of the interval of the actually used video signal. an input example is shown below. [1] input every h sync i n p u t c l k c a l 2. latch-up ensure that the av dd and dv dd pins share the same power supply on a board to prevent latch-up which may be caused by power-on time lag. 3. board to obtain full-expected performance from this ic, be sure that the mounting board has a large ground pattern for lower impedance. it is recommended that the ic be mounted on a board without using a socket to evaluate its characteristics adequately.
? 15 CXD3300R example of representative characteristics 2 0 1 8 1 6 1 4 4 0 0 2 5 5 0 8 5 a m b i e n t t e m p e r a t u r e [ c ] s u p p l y c u r r e n t [ m a ] s u p p l y c u r r e n t v s . a m b i e n t t e m p e r a t u r e a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 0 m h z f i n = 1 k h z s i n e w a v e 3 8 3 6 3 4 3 2 4 0 0 2 5 5 0 8 5 a m b i e n t t e m p e r a t u r e [ c ] m a x i m u m o p e r a t i n g f r e q u e n c y [ m h z ] m a x i m u m o p e r a t i n g f r e q u e n c y v s . a m b i e n t t e m p e r a t u r e a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 0 m h z f i n = 1 k h z s i n e w a v e 1 1 1 0 9 8 4 0 0 2 5 5 0 8 5 a m b i e n t t e m p e r a t u r e [ c ] o u t p u t d a t a d e l a y [ n s ] o u t p u t d a t a d e l a y v s . a m b i e n t t e m p e r a t u r e a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 m h z c l = 3 0 p f 8 6 4 2 4 0 0 2 5 5 0 8 5 a m b i e n t t e m p e r a t u r e [ c ] s a m p l i n g d e l a y [ n s ] s a m p l i n g d e l a y v s . a m b i e n t t e m p e r a t u r e a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 m h z 2 . 0 1 . 9 5 1 . 9 0 1 . 8 5 4 0 0 2 5 5 0 8 5 a m b i e n t t e m p e r a t u r e [ c ] v r t c [ v ] v r t c v s . a m b i e n t t e m p e r a t u r e a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 0 m h z f i n = 1 k h z s i n e w a v e 1 . 2 0 1 . 1 5 1 . 1 0 1 . 0 5 4 0 0 2 5 5 0 8 5 a m b i e n t t e m p e r a t u r e [ c ] v r b c [ v ] v r b c v s . a m b i e n t t e m p e r a t u r e a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 0 m h z f i n = 1 k h z s i n e w a v e
? 16 CXD3300R 7 0 6 0 5 0 4 0 1 0 0 k 1 m 1 0 0 m a n a l o g i n p u t f r e q u e n c y [ h z ] s n r [ d b ] s n r v s . a n a l o g i n p u t f r e q u e n c y a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 0 m h z v i n = 1 v p - p t a = 2 5 c 7 0 6 0 5 0 4 0 1 0 0 k 1 m 1 0 0 m a n a l o g i n p u t f r e q u e n c y [ h z ] s f d r [ d b ] s f d r v s . a n a l o g i n p u t f r e q u e n c y a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 0 m h z v i n = 1 v p - p t a = 2 5 c 8 7 6 1 0 0 k 1 m 1 0 0 m a n a l o g i n p u t f r e q u e n c y [ h z ] e f f e c t i v e b i t [ b i t ] e f f e c t i v e b i t v s . a n a l o g i n p u t f r e q u e n c y a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 0 m h z v i n = 1 v p - p t a = 2 5 c 5 m 1 0 m 5 0 m 7 5 m 8 5 m a n a l o g i n p u t f r e q u e n c y [ h z ] o u t p u t l e v e l [ d b ] a n a l o g i n p u t b a n d 1 0 0 m 1 1 2 3 0 a v d d = 3 . 0 v d v d d = 3 . 0 v f c = 2 0 m h z v i n = 1 v p - p t a = 2 5 c
? 17 CXD3300R package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 4 8 p i n l q f p ( p l a s t i c ) 9 . 0 0 . 2 * 7 . 0 0 . 1 1 1 2 1 3 2 4 2 5 3 6 3 7 4 8 ( 0 . 2 2 ) 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 2 g l q f p - 4 8 p - l 0 1 l q f p 0 4 8 - p - 0 7 0 7 ( 8 . 0 ) 0 . 5 0 . 2 0 . 1 2 7 0 . 0 2 + 0 . 0 5 a 1 . 5 0 . 1 + 0 . 2 0 . 1 s o l d e r / p a l l a d i u m n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 d e t a i l a 0 . 1 3 m 0 . 5 s s b d e t a i l b : s o l d e r ( 0 . 1 8 ) ( 0 . 1 2 7 ) d e t a i l b : p a l l a d i u m 0 . 1 2 7 0 . 0 4 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 1 2 7 0 . 0 2 + 0 . 0 5 0 . 1 8 0 . 0 3

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